Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Device dimensions in CMOS technology, the dominant technology used for digital logic and semiconductor memories, have been scaled in the past few decades to achieve improved performance particularly in terms of speed of operation, dynamic power dissipation, and packing density of the logic and memory devices. In CMOS design, various design parameters can be adjusted to realize a practical implementation. Example design parameters may include the OFF-State leakage current, low, which indicates the leakage power dissipation; and the ON-state current. ION, which impacts the speed of operation. In some designs it may be desired to maintain IOFF as low as possible while also maintaining ION as high as possible, resulting in the ratio of ION/IOFF being maintained as high as possible. In order to achieve high values of ION and low values of IOFF (or high ION and a high ION/IOFF ratio), the sub-threshold swing of the device, which may be defined as the gate voltage shift needed to change the drain current by one order of magnitude (one decade), may be low.
In practical CMOS designs, short-channel effects such as Drain Induced Barrier Lowering (DIBL) may cause a substantial increase in IOFF due to dimension scaling (decrease of dimensions proportionally). The supply voltage VDD may also need to be decreased in order to reduce power density and short-channel effects. Decreased values of VDD may need a reduction in the threshold, voltage, VT, in order to achieve commensurate device performance. Sub-threshold swing, SS, may have a fundamental physical limit of 60 mV/decade ((kT/q)*ln(10)) for a conventional MOSFET at room temperature. Due to this limitation, efforts to reduce values of VDD may further increase the leakage current and, therefore, VDD may not be able to be practically scaled much further below 1.0 V or so for conventional CMOS technology.
In the search for an alternative CMOS-compatible device with a low sub-threshold swing SS to maintain high ION with an acceptable IOFF for further extending Moore's law for digital and memory applications, tunnel field-effect transistors (TFETs) have shown promise. Conventional injection mechanisms of TFETs tray be based on a band-to-band tunneling (BTBT) mechanism in contrast to the thermal injection mechanism of a conventional MOSFET that poses the fundamental SS limitation of 60 mV/decade on such devices.
In spite of their desired low SS, conventional TFETs typically have a low ON-state current, ION. Various improvements in ION performance of TFETs have been reported through the use of lower band-gap material such as SiGe or Ge in the tunneling region. Various improvements include the use of double-gale architectures, high-k gate dielectrics, thin silicon bodies, and similar approaches. However, these types of improvements do not meet the industry needs of high ION for sub-0.5V operation.